module CodePattern(
    input               clk100M,
    input               clk200M,
    input               rst_n,
    input       [15:0]  dataIn,
    input       [9:0]   wr_addr,
    input               wr_en,
    input       [9:0]   max_addr,
    input               dinaclr,

    input       [31:0]  data_range,
    input       [31:0]  pulse_range,
    input       [13:0]  dioin,
    input               rd_code,
    output      [1:0]   DIO_IN,

    input       [1:0]   PatternIn,
    output  reg [15:0]  PatternOut
);

reg[9:0] rd_addr;
wire[15:0] dataOut;
BRAM RAMW(
	.wrclock(clk200M),
	.data(dataIn),
	.wraddress(wr_addr),
	.wren(wr_en),
	.rdclock(clk200M),
	.rdaddress(rd_addr),
	.q(dataOut)
);

//以10ns为单位调整
// reg[31:0] pulse_cnt;
// always @(posedge clk100M or negedge rst_n) begin
//    if (!rst_n) begin
//        PatternOut   <= 16'h0;
//        pulse_cnt    <= 32'h0;
//        rd_addr      <= 10'h0;
//    end else begin
//        if (pulse_cnt < data_range) begin
//            if (pulse_cnt > pulse_range) begin
//                PatternOut   <= 16'h0;
//            end else begin
//                PatternOut   <= dataOut;
//            end
//            pulse_cnt    <= pulse_cnt + 1'b1;
//        end else begin
//            if (rd_addr < max_addr) begin
//                rd_addr      <= rd_addr + 1'b1;
//                pulse_cnt    <= 32'h0;
//            end else begin
//                pulse_cnt    <= pulse_cnt;
//            end
//        end
//    end
// end

reg[31:0] pulse_cnt;
always @(posedge clk100M or negedge rst_n) begin
   if (!rst_n) begin
       PatternOut   <= 16'h0;
       pulse_cnt    <= 32'h0;
       rd_addr      <= 10'h0;
   end else begin
       if (pulse_cnt < data_range) begin
           if ((pulse_cnt == (data_range - 1'b1)) && (pulse_cnt > pulse_range)) begin
               rd_addr      <= rd_addr + 1'b1;
               PatternOut   <= 16'h0;
           end else if ((pulse_cnt > pulse_range) && (pulse_cnt != (data_range - 1'b1))) begin
               PatternOut   <= 16'h0;
           end else if ((pulse_cnt == (data_range - 1'b1)) && (pulse_cnt == pulse_range)) begin
               rd_addr      <= rd_addr + 1'b1;
               PatternOut   <= dataOut;
           end else begin
               PatternOut   <= dataOut;
           end
           pulse_cnt    <= pulse_cnt + 1'b1;
       end else begin
           if (rd_addr <= max_addr) begin
               pulse_cnt    <= 32'h0;
           end else begin
               pulse_cnt    <= pulse_cnt;
           end
           PatternOut   <= 16'h0;
       end
   end
end


/*--------------------------------采样率控制--------------------------------*/
/*--------------------------------采样率控制--------------------------------*/
/*--------------------------------采样率控制--------------------------------*/
wire wr_fifo;//FIFO写时钟 实际采样率
reg clkfisp;
reg[13:0] divict;
assign wr_fifo = |dioin ? clkfisp : clk100M;
always@(posedge clk100M)
begin
	if(!rst_n)
	begin
		clkfisp	<= 1'b0;
		divict	<= 14'h1;
	end
	else
	begin
		if(divict == dioin)
		begin
			clkfisp	<= 1'b1;
			divict	<= 14'h1;
		end
		else
		begin
			clkfisp	<= 1'b0;
			divict	<= divict + 1'b1;
		end
	end
end


FIFO2 FIFOR(
    .aclr(dinaclr),
	.data(PatternIn),
	.wrclk(wr_fifo),
	.wrreq(1'b1),
	.rdclk(rd_code),
	.rdreq(1'b1),
	.q(DIO_IN),
	.rdempty(),
	.wrfull()
);


endmodule
